View AD7091_9087619.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 msps, ultralow power, 12-bit adc in 8-lead lfcsp data sheet AD7091 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2012C2013 analog devices, inc. all rights reserved. technical support www.analog.com features fast throughput rate of 1 msps specified for v dd of 2.09 v to 5.25 v inl of 1 lsb maximum analog input range of 0 v to v dd ultralow power 367 a typical at 3 v and 1 msps 324 na typical at 3 v in power-down mode reference provided by v dd flexible power/throughput rate management high speed serial interface: spi?-/qspi?-/microwire?-/ dsp-compatible busy indicator power-down mode 8-lead, 2 mm 2 mm lfcsp package temperature range: ?40c to +125c applications battery-powered systems handheld meters medical instruments mobile communications instrumentation and control systems data acquisition systems optical sensors diagnostic/monitoring functions energy harvesting functional block diagram conversion control logic gnd clk osc v in regcap v dd 12-bit sar adc serial interface sdo AD7091 sclk cs convst t/h 10494-001 figure 1. 0 100 200 300 400 500 600 700 800 900 1000 1100 0 200 400 600 800 1000 power ( w) throughput rate (ksps) v dd = 3v 10494-002 figure 2. power dissipation vs. throughput rate general description the AD7091 is a 12-bit successive approximation register analog-to-digital converter (sar adc) that offers ultralow power consumption (typically 367 a at 3 v and 1 msps) while achieving fast throughput rates (1 msps with a 50 mhz sclk). the AD7091 operates from a single 2.09 v to 5.25 v power supply. the AD7091 also features an on-chip conversion clock and a high speed serial interface. the conversion process and data acquisition are controlled using a convst signal and an internal oscillator. the AD7091 has a serial interface that allows data to be read after the conversion while achieving a 1 msps throughput rate. the AD7091 uses advanced design and process techniques to achieve very low power dissipation at high throughput rates. the reference is derived internally from v dd . this design allows the widest dynamic input range to the adc; that is, the analog input range for the AD7091 is from 0 v to v dd . product highlights 1. lowest power 12-bit sar adc available. 2. high throughput rate with ultralow power consumption. 3. flexible power/throughput rate management. average power scales with the throughput rate. power-down mode allows the average power consumption to be reduced when the device is not performing a conversion. 4. reference derived from the power supply. 5. single-supply operation.
important links for the AD7091 * last content update 11/13/2013 03:16 pm similar products & parametric selection tables find similar products by operating parameters low resolution - single channel unipolar/bipolar 8/10/12-bit pulsar adcs documentation an-1141: powering a dual supply precision adc with switching regulators an-931: understanding pulsar adc support circuitry an-935: designing an adc transformer-coupled front end the data conversion handbook mt-001: taking the mystery out of the infamous formula, snr=6.02n + 1.76db, and why you should care ug-447: evaluation board for the AD7091 analog-to-digital converter suggested companion products recommended driver amplifiers for the AD7091 for low frequency and low bias current, we recommend the ada4627-1, ada4637-1 or the ad8610 . for precision, low power, rail-to-rail output, we recommend the ada4841-1, ada4896-2 or the ad8031 . for high frequency, low noise, low distortion, we recommend the ada4899-1, ada4897-1 or the ad8021 . for additional driver amplifier selections , we recommend selecting the product category and filtering on our parametric search tables. recommended external references for vdd for the AD7091 for a 3v, low power, low noise, we recommend the adr4530 or the ref193 . for a 5v, low power, low noise, we recommend the adr4550 or the ref195 . for additional voltage reference selections , we recommend filtering on our parametric search tables. design tools, models, drivers & software AD7091 ibis model evaluation kits & symbols & footprints view the evaluation boards and kits page for the AD7091 view the evaluation boards and kits page for the AD7091r symbols and footprints design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy AD7091 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
AD7091 data sheet rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 4 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 terminology ...................................................................................... 9 theory of operation ...................................................................... 10 circuit information .................................................................... 10 converter operation .................................................................. 10 adc transfer function ............................................................. 10 typical connection diagram ................................................... 11 analog input ............................................................................... 11 modes of operation ................................................................... 12 power consumption .................................................................. 13 multiplexer applications ........................................................... 14 serial interface ................................................................................ 15 busy indicator enabled .............................................................. 15 busy indicator disabled ............................................................ 16 software r eset ............................................................................. 17 interfacing with an 8 - /16 - bit spi bus ...................................... 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 6 /13 rev. 0 to rev. a changes to figure 22 ...................................................................... 13 added multiplexer applications section .................................... 14 updated outline dimensions ....................................................... 18 10 /12 revision 0 : initial version
data sheet AD7091 rev. a | page 3 of 20 specifications v dd = 2.09 v to 5 .25 v , f sample = 1 msps, f sclk = 5 0 mhz, t a = ?40c to +125c , unless otherwise noted. table 1 . parameter test conditions/comments min typ max unit dynamic performance 1 f in = 10 khz sine wave signal -to - noise ratio (snr) 2 v dd < 2.7 v 68 db v dd 2.7 v 67 69 db signal -to - noise - and - distortion ratio (sinad) 2 66. 3 6 8 db total harmonic distortion (thd) 2 ? 86 ? 74 db spurious - free dynamic range (sfdr) 2 ?85 ? 75 db aperture delay 2 5 ns aperture jitter 2 40 ps full power bandwidth 2 at ?3 db 1 .5 mhz at ?0.1 db 1.2 mhz dc accuracy resolution 12 bits integral nonlinearity (inl) 2 0. 6 1 lsb differential nonlinearity (dnl) 2 guaranteed no missing codes to 12 bits 0. 3 0.9 lsb offset error 2 ? 8 . 5 0.7 + 5 lsb gain error 2 1 .2 4 lsb total unadjusted error (tue) 2 1 .1 lsb analog input input voltage range 0 v dd v dc leakage current 1 a input capacitanc e 3 during ac quisition phase 7 pf outside acquisition phase 1 pf logic inputs input high voltage (v inh ) 0.7 v dd v input low voltage (v inl ) 0.3 v dd v input current (i in ) typically 10 na, v in = 0 v or v dd 1 a input capacitance (c in ) 3 5 pf logic outputs output high voltage (v oh ) i source = 200 a v dd ? 0.2 v output low voltage (v ol ) i sink = 200 a 0.4 v floating state leakage current 1 a floating state output capacitance 3 5 pf output coding straight binary conversion rate conversion time 6 5 0 ns track - and - hold acquisition time 2 , 3 full - scale step input 3 5 0 ns throughput rate 1 msps power requirements v dd 2.09 5 .25 v i dd v in = 0 v normal mode static 4 v dd = 5.25 v 9. 3 2 7 a v dd = 3 v 9.1 28 a normal mode operational v dd = 5.25 v , f sample = 1 msps 4 50 554 a v dd = 3 v, f sample = 1 msps 367 4 42 a v dd = 3 v, f sample = 100 ksps 4 5 a power - down mode v dd = 5.25 v 0.3 7 4 8 .2 a v dd = 3 v 0.32 4 8 a v dd = 3 v, t a = ?40c to +85c 0.32 4 1.8 a
AD7091 data sheet rev. a | page 4 of 20 parameter test conditions/comments min typ max unit power dissipation v in = 0 v normal mode static 4 v dd = 5 .25 v 5 0 1 4 2 w v dd = 3 v 27 84 w normal mode operational v dd = 5 .25 v , f sample = 1 msps 2. 4 3 mw v dd = 3 v, f sam ple = 1 msps 1 .1 1. 4 mw power - down mode v dd = 5 .25 v 2 4 4 w v dd = 3 v 1 24 w 1 dynamic performance is achieved when sclk operat es in burst mode. operating a free running sclk during the acq uisition phase degrades dynamic performance. 2 see the terminology se ction. 3 sample tested during initial release to ensure compliance. 4 sclk is operating in burst mode and cs is idling high. with a f ree running sclk and cs pulled low, the i dd static current is increased by 6 0 a typical at v dd = 5.25 v . timing specification s v dd = 2.09 v to 5 .25 v , t a = ?40c to +125c , unless otherwise note d. signals are specified from 10% to 90 % of v dd with a load capacitance of 12 pf on the output pin . 1 table 2 . parameter limit at t min , t max unit description f sclk 5 0 mhz max frequency of serial read clock t 1 8 ns max delay from the end of a conversion until sdo exits the three - state condition t 2 7 ns max d ata access time after sclk falling edge t 3 0.4 t sclk ns min sclk high pulse width t 4 3 ns min sclk to data valid hold time t 5 0.4 t sclk ns min sclk low pulse width t 6 15 ns max sclk falling edge to sdo high impedance t 7 1 0 ns min convst pulse width t 8 6 5 0 ns max conversion time t 9 6 ns min cs low time before the end of a conversion t 10 1 8 ns max delay from cs falling edge until sdo exits the three - state condition t 11 8 ns min cs high time before the end of a conversion t 12 8 ns min delay from the end of a conversion until the cs falling edge t 13 1 00 s max power - up time t quiet 50 ns min time between the last sclk edge and the next convst pu lse 1 sample tested during initial release to ensure compliance.
data sheet AD7091 rev. a | page 5 of 20 absolute maximum rat ings t a = 25c, unless otherwise noted . table 3 . parameter rating v dd to gnd ?0.3 v to +7 v analog input voltage to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v digit al output voltage to gnd ?0.3 v to v dd + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c esd human body model ( hbm ) 2.5 kv fiel d - induced charged device model ( ficdm ) 1.5 kv 1 transient currents of up to 100 ma do not cause silicon controlled rectifier (scr) latch - u p. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect de vice reliability. thermal resistance table 4 . thermal resistance package type ja jc unit 8 - lead lfcsp 36.67 6.67 c/w esd caution
AD7091 data sheet rev. a | page 6 of 20 pin configuration an d function descripti ons notes 1. the exposed pad is not connected internally. for increased reliability of the solder joints and for maximum thermal capability, solder the exposed pad to the substrate, gnd. 3 regca p 4 gnd 1 v dd 2 6 cs 5 convst 8 sdo 7 sclk v in 10494-003 AD7091 top view (not to scale) figure 3 . pin co nfiguration table 5 . pin function descriptions pin no. mnemonic description 1 v dd power supply input. the v dd range is from 2.09 v to 5 .25 v . d ecouple t his supply pin to gnd. typical recom - mended capacitor values are 10 f and 0.1 f. 2 v in analog input. the single - ended analog input range is from 0 v to v dd . 3 regcap decoupling capacitor pin for voltage output from internal low dropout (ldo) regulator. d ecouple t his output pin separately to gnd using a 1 f capacitor. the voltage at this pin is 1.8 v typical . 4 gnd ground. this pin is the ground reference point for all circuitry on the AD7091 . the analog input signal should be refer red to this gnd voltage. 5 convst conver sion start. active low , edge triggered logic input. the falling edge of convst places the track - and - hold into hold mode and initiates a conversion. 6 cs chip se lect. active low logic input. the serial bus is enabled when cs is held low; in this mode cs is used to frame the output data on the spi bus. 7 sclk serial clock. this pin acts as the serial clock input. 8 sdo serial d ata output. the conversion output data is supplied to this pin as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data is provided msb first. 9 epad exposed pad. the exposed pad is not connected internally. for in creased reliability of the solder joints and for maximum thermal capability, solder the exposed pad to the substrate, gnd.
data sheet AD7091 rev. a | page 7 of 20 typical performance characteristics ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 100 200 300 400 500 amplitude (db) frequenc y (khz) v dd = 3v t a = 25c f in = 10khz f sample = 1msps snr = 69.84db sinad = 69.56db thd = ?81.05db 10494-004 figure 4 . typical dynamic performance ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 in l (lsb) code v dd = 3v t a = 25c f sample = 1msps 10494-005 figure 5. typical inl performance ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 dn l (lsb) code v dd = 3v t a = 25c f sample = 1msps 10494-006 figure 6 . typical dnl performance 60 62 64 66 68 70 72 1 10 100 snr (db) input frequenc y (khz) t a = 25c f sample = 1msps 10494-007 v dd = 2.7v v dd = 5v v dd = 3v figure 7 . snr vs. analog input frequency for various supply voltages ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1 10 100 thd (db) input frequenc y (khz) v dd = 2.7v v dd = 3v t a = 25c f sample = 1msps 10494-008 figure 8 . thd vs. analog input frequency for various supply voltages ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 10 100 1000 10000 thd (db) source impedance () v dd = 3v t a = 25c f in = 10khz f sample = 1msps 10494-009 figure 9. t hd vs. source impedance
AD7091 data sheet rev. a | page 8 of 20 50 55 60 65 70 75 1 10 100 sinad (db) input frequenc y (khz) v dd = 2.7v t a = 25c f sample = 1msps 10494-010 v dd = 3v v dd = 5v figure 10. sinad vs. analog input frequency for various supply voltages 60 50 40 30 20 10 0 number of occurrences (k) code 2047 2048 2049 2050 2051 8108 5992 51,436 v dd = 3.3v t a = 2 5 c 65,536 samples 0 0 10494-0 1 1 figure 11 . histogram of codes at code center (v dd /2) 7 6 5 4 3 2 1 0 10 20 30 40 50 t 2 del a y (ns) sdo ca p aci t ance load (pf) ?40c +25c +125c v dd = 3v 10494-012 figure 12. t 2 delay vs. sdo capacitance load, v d d = 3 v 250 300 350 400 450 500 550 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.50 4.25 4.75 5.00 supply current (a) supp l y vo lt age (v) ?40c f sample = 1msps +125c 10494-013 +25c +85c figure 13 . operational supply current vs. supply voltage for various temperatures 0 1000 2000 3000 4000 5000 6000 supply current (na) temper a ture (c) v dd = 2.09v v dd = 3v v dd = 3.6v v dd = 5.25v ?40 25 85 125 10494-014 figure 14 . power - down supply current vs. temperature for various supply voltages
data sheet AD7091 rev. a | page 9 of 20 terminology integral nonlinearity (inl) inl is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. for the AD7091 , the endpoints of the transfer function are zero scale (a point 0.5 lsb below the first code transition) and full scale (a point 0.5 lsb a bove the last code transition). differential nonlinearity (dnl) dnl is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error offset error is the deviation of the first code transition (00 000 to 00 001) from the ideal (such as gnd + 0.5 lsb). gain error gain err or is the deviation of the last code transition (111 110 to 111 111) from the ideal (such as v dd ? 1.5 lsb) after the offset error has b een adjusted out. track - and - hold acquisition time the track - and - hold amplifier returns to track mode after the end o f a conversion. the track - and - hold acquisition time is the time required for the output of the track - and - hold amplifier to reach its final value, within 0.5 lsb, after a conversion . signal -to - noise ratio (snr) snr is the measured ratio of signal to noise at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequen cy (f sample /2), excl uding dc. the ratio is dependent on the number of quantization levels in the dig itization process: the more levels, the smaller the quantization noise. the theoretical signal - to - noise ratio for an ideal n - bit converter wit h a sine wave input is given by signal - to - noise ratio = ( 6.02 n + 1.76 ) db therefore, for a 12 - bit convert er, the s n r is 74 db. signal -to - noise - and - distortion ratio (sinad) sinad is the measured ratio of signal to noise and distortion at the output of the adc. the signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f sample /2), including harmonics, but excluding dc. total unadjusted error (tue) tue is a comprehensive specification that includes the gain, linearity, and offset errors. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the funda - mental. for the AD7091 , thd is defined as ( ) 1 6 5 4 3 2 v v v v v v thd 2 2 2 2 2 log 20 db + + + + = where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. spurious - free dynamic range (sfdr) sfdr, also known as peak harmonic or spurious noise, is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f sample /2 and excluding dc) to th e rms value of the fundamental. aperture delay aperture delay is the measured interval between the leading edge of the sampling clock and the point at which the adc samples data. aperture jitter aperture jitter is the sample - to - sample variation in the effe ctive point in time at which the data is sampled . full power bandwidth full power bandwidth is the input frequency at which the ampli - tude of the reconstructed fundam ental is reduced by 0.1 db or 3 db for a full - scale input.
AD7091 data sheet rev. a | page 10 of 20 theory of operation circuit information the AD7091 is a 12 - bit successive approximation register analog - to - digital converter ( sar adc) that offers ultralow power consumption (typically 3 67 a at 3 v and 1 msps) while achieving fast t hrou ghput rates (1 msps with a 5 0 mhz sclk). the part operate s from a single power supply in the range of 2.09 v to 5 .25 v . the AD7091 provides an on - chip track - and - hold amplifier and an analog - to - digital converte r (adc) with a serial interface housed in a tiny 8 - lead lfcsp package. this package offers considerable space - saving advantages compared with alternative solutions. the serial clock input accesses data from the part. the clock for the sar adc is generated internally. the analog input range is 0 v to v dd . an external reference is not required for the adc, nor is there a reference on chip. the reference voltage for the AD7091 is derived from the power supply and , thus , provides the widest dynamic input range of 0 v to v dd . the AD7091 also features a power - down option to save power between conversions. the power - down feature is implemented using the standard serial inter face , as described in the modes of operation section. converter operation the AD7091 is a sar adc based around a charge redistribu - tion dac. figure 15 and figure 16 show simplified schematics of the adc. figure 15 shows the adc during its acquisition phase ; sw2 is closed and sw1 is in position a . t he comparator is held in a balanced condition, and the sam pling capacitor acquires the signal on v in . charge redistribution dac control logic comparator sw2 sampling capacitor acquisition phase sw1 a b gnd ldo/2 v in 10494-015 figure 15 . adc acquisition phase when the adc starts a conversion, sw2 opens and sw1 moves to position b, causing the comparator to become unbalanced (see figure 16) . the control logic and the charge redistribution dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion i s complete. the control logic generates the adc output code. figure 17 show s the adc transfer function. charge redistribution dac control logic comparator sw2 sampling capacitor conversion phase sw1 a b gnd ldo/2 v in 10494-016 figure 16 . adc conversion phase adc transfer function the output coding of the AD7091 is straight binary. the designed code transitions occur midway between successive integer lsb values, such as 0.5 lsb, 1.5 lsb, and so on. the lsb size for the AD7091 is v dd /409 6. the ideal transfer characteristic for the AD7091 is shown in figure 17 . 000 ... 000 0v adc code analog input 111 ... 111 000 ... 001 000 ... 010 111 ... 110 111 ... 000 011 ... 111 1lsb v dd ? 1lsb 1lsb = v dd /4096 10494-017 figure 17 . AD7091 transfer characte ristic
data sheet AD7091 rev. a | page 11 of 20 typical connection diagram figure 19 shows a typical connection diagram for the AD7091. a positive power supply in the range of 2.09 v to 5.25 v should be connected to the v dd pin. the reference is derived internally from v dd and, for this reason, v dd should be well decoupled to achieve the specified performance; typical values for the decoupling capacitors are 100 nf and 10 f. the analog input range is 0 v to v dd . the typical value for the regulator bypass decoupling capacitor (regcap) is 1 f. the conversion result is output in a 12-bit word with the msb first. alternatively, because the supply current required by the AD7091 is so low, a precision reference can be used as the supply source to the part. a reference from the ref19x or adr34xx voltage reference family ( ref195 or adr3450 for 5 v, and ref193 or adr3430 for 3 v) can be used to supply the required voltage to the adc. this configuration is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 v or 3 v, such as 15 v. if the busy indicator function is required, connect a pull-up resistor of typically 100 k to v dd to the sdo pin (see figure 19). in addition, for applications in which power consumption is a concern, the power-down mode can be used to improve the power performance of the adc (see the modes of operation section for more information). analog input figure 18 shows an equivalent circuit of the AD7091 analog input structure. the d1 and d2 diodes provide esd protection for the analog input. to prevent the diodes from becoming forward-biased and conducting current, ensure that the analog input signal never exceeds v dd by more than 300 mv. these diodes can conduct a maximum of 10 ma without causing irreversible damage to the part. d1 d2 r1 c2 3.6pf v dd v in c1 1pf c3 2.5pf notes 1. during the conversion phase, the switch is open. during the track phase, the switch is closed. 10494-019 figure 18. equivalent analog input circuit capacitor c1 in figure 18 is typically about 1 pf and can primarily be attributed to pin capacitance. resistor r1 is a lumped component made up of the on resistance of a switch. this resistor is typically about 500 . capacitor c2 is the adc sampling capacitor and typically has a capacitance of 3.6 pf. in applications where harmonic distortion and signal-to-noise ratio (snr) are critical, the analog input should be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc and may necessitate the use of an input buffer amplifier, as shown in figure 19. the choice of the op amp is a function of the particular application. when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. th e thd increases as the source impedance increases and performance degrades. figure 9 shows a graph of thd vs. source impedance when using a supply voltage of 3 v and a sampling rate of 1 msps. to achieve the specified performance, use an external filtersuch as the one-pole, low-pass rc filter shown in figure 19on the analog input connected to the AD7091. AD7091 v in gnd convst sdo v dd cs sclk regcap microprocessor/ microcontroller/ dsp 10 f 100nf 1 f 100k ? with busy indicator analog input v dd v dd 51 ? 4.7nf (2.09v to 5.25v) 10494-018 figure 19. typical connection diagram
AD7091 data sheet rev. a | page 12 of 20 modes of operation the mode of operat ion of the AD7091 is selected by controlling the logic level of the convst signal when a conversion is complete. the two modes of operation are normal mode and power - down mode . these modes of operation provide flexible power manage - ment options, allowing optimization of the power dissipation to throughput rate ratio for different application requirements. the logic level of the convst pin at the end of a conversion determines whether the AD7091 remains in normal mode or enters power - down mode (see the normal mode section and the power - down mode section). similarly, if the device is in power - down mode, convst controls whether the device returns to normal mode or remains in power - down mode. normal mode the normal mode of operation is intended to achieve the fastest throughput rate performance. in normal mode, the AD7091 remains fully powered at all times, so power - up times are not a concern . figure 20 shows the general timing diagram of the AD7091 in normal mode. in normal mode, the conversion is initiated on the falling edge of convst , as described in the serial interface section. to ensure that the part remains fully powered at all times, convst must return high after t 7 and remain h igh until the conversion is com - plete. at the end of a conversion (denoted as eoc in figure 20 ), the logic level of convst is tested. to read back data stored in the conversion result register, wait until the conversion is complete, and then pull cs low. the conversion data is subsequently clocked out on the sdo pin (see figure 20 ). because the output shift register is 1 2 bits wide, data is shifted out of the device as a 12 - bit word under the control of the serial clock input (sclk). after reading back the data, the user can pull convst low again to start another conversion after the t quiet time has elap sed. power - down mode the power - down mode of operation is intended for use in applica - tions where slower throughput rates and lower power consumption are required. in this mode, the adc can be powered down after each conversion or after a series of conversi ons performed at a high t hroughput rate, with the adc powered down for relatively long durations between these bursts of several conversions. when the AD7091 is in power - down mode, the serial interface remains active even though all analog circuitry is powered down. to enter power - down mode, pull convst low and keep it low prior to the end of a conversion (denoted as eoc in figure 21). after the conversion is complete , the logic level o f the convst pin is tested. if the convst signal is logic low, the part enters power - down mode. the serial interface of the AD7091 is functional in power - d own mode; therefore, users can read back the conversion result after the part enters power - down mode. notes 1 . is don?t care. t 8 convst t 7 conversion data t 10 cs sdo eoc t 12 2. eoc is the end of a conversion. 10494-026 figure 20 . normal mode of operation, serial interface read timing t 8 convst conversion data t 10 cs sdo eoc power-down mode t 12 t 13 10494-027 notes 1 . is don?t care. 2. eoc is the end of a conversion. figure 21 . entering and exitin g power - down mode
data sheet AD7091 rev. a | page 13 of 20 to exit power - down mode and power up the AD7091 , pull convst high at any time. on the rising edge of convst , the device begins to power up. the power - up t ime of the AD7091 is 10 0 s. to start the next conversion, operate the interface as described in the normal mode section. power consumption the two modes of operation for the AD7091 normal mode and power - down mode (see the modes of operation section for more information) produce different power vs. throughput rate performances. using a combination of normal mode a nd power - down mode achieves the optimum power performance. to achieve optimum static current consumption , sclk should be in burst mode and cs should idle high. failure to adhere to these guidelines results in increased static current. imp roved power consumption for the AD7091 can also be achieved by carefully selecting the v dd supply (see figure 13). power consumption in normal mode with a 3 v v dd supply and a through put rate of 1 msps, the i dd current consumption for the part in normal operational mode is 3 67 a (composed of 9.1 a of static current and 3 57.9 a of dynamic current during conversion). the dynamic current con - sumption is directly proportional to the throughput rate. the following example calculates the power consumption of the AD7091 when operating in normal mode with a 500 ksps throughput rate and a 3 v supply. t he dynamic conversion time contributes 537 w to the overall power dissipation as follows : ((500 ksps/1 msps) 357.9 a) 3 v = 537 w the contribution to the total power dissipated by the normal mode static operation is 9.1 a 3 v = 27 w therefore, the total power dissipated at 500 ksps is 537 w + 27 w = 564 w power consumption using a combination of normal mode and power - down mode a combination of n ormal m ode and p ower - d own m ode achieves the optimum power performance. this operation can be performed at consta nt sampling rates of < 1 0 ksps. figure 22 shows the ad709 1 conversion sequence using a combination of n ormal m ode and power - down mode with a throughput of 5 ksps. with a v dd supply voltage of 3 v, the static current is 9.1 a. the dynamic current is 357.9 a at 1 msps. the current consumption during p ower - d own mode is 324 na. a conversion takes typically 6 5 0 ns to complete , and the AD7091 takes 10 0 s to power up from power - down mode . the dynamic conversion time contributes 5 w to the overall power dissipation as follows: ((5 ksps/1 msps) 357.9 a ) 3 v = 5 w the contribution to the total power dissipated by the normal mode static operation and the p ower - down mode is (((100 s + 6 5 0 ns ) / 2 00 s) 9.1 a) 3 v + ((9 9. 4 s / 2 00 s) 324 na) 3 v = 14 w therefore, the total power dissipated at 5 ksps is 5 w + 14 w = 19 w 99 s power-down 100 s power-up 650ns conversion 200 s c o n vs t eoc c s sdo d a t a 10494-022 notes 1. eoc is the end of a conversion. figure 22 . conversion sequence with normal mode and power - down mode , 5 ks ps throughput
AD7091 data sheet rev. a | page 14 of 20 figure 23 and figure 24 show the typical power dissipation vs. throughput rate for the AD7091 at 3 v for the v dd supply. figure 24 show s the reduction in power consumption that can be achieved when power - down mode is used compared with using only normal mode at lower throughput rates. 0 100 200 300 400 500 600 700 800 900 1000 1 100 0 200 400 600 800 1000 power (w) throughput r a te (ksps) v dd = 3v 10494-124 figure 23 . power dissipation vs. throughput rate (full r ange) 1 10 100 0.01 0.1 1 10 100 power (w) throughput r a te (ksps) v dd (no pd) v dd = 3v v in = 0v v dd 10494-123 figure 24 . power dissipation vs. t hroughput rate (lower range) multiplexer applicat ions a multiplexer can be used in the signal chain to switch multiple analog input signals to the AD7091 . in such applications, control the multiplexer switch time to ensure accurate analog - to digital - conversion of the input signals. to allow the AD7091 to fully acquire the input signal, the multiplex er should switch in the channel to be converted a minimum of 350 ns before initiating a conversion. the multiplexer should also hold th is channel at the AD7091 for a minimum of 200 ns after the c onvst falling edge.
data sheet AD7091 rev. a | page 15 of 20 serial interface the AD7091 serial interface consists of four signals: sclk, sdo, convst , and cs . the serial interface is used to access data from the result register and to control the modes of oper- ation of the device. ? the sclk pin is the serial clock input for the device. ? the sdo pin outputs the conversion result; data transfers take place with respect to sclk. ? the convst pin is used to initiate the conversion process and to select the mode of operation of the AD7091 (see the modes of operation section). ? the cs pin is used to frame the data. the falling edge of cs takes the sdo line out of a high impedance state. a rising edge on cs returns the sdo line to a high impedance state. the logic level of cs at the end of a conversion determines whether the busy indicator is enabled. this feature affects the propagation of the msb with respect to cs and sclk. busy indicator enabled when the busy indicator is enabled, the sdo pin can be used as an interrupt signal to indicate that a conversion is complete. the connection diagram for this configuration is shown in figure 25. note that a pull-up resistor to v dd is required on the sdo pin. data in irq clk convert v dd digital host 100k ? convst sclk sdo cs AD7091 cs1 10494-023 figure 25. connection diagram with busy indicator the busy indicator allows the host to detect when the sdo pin exits the three-state condition after the end of a conversion. when the busy indicator is enabled, 13 sclk cycles are required: 12 clock cycles to propagate the data and an additional clock cycle to return the sdo pin to the three-state condition. to enable the busy indicator feature, a conversion must first be started. a high-to-low transition on convst initiates a conversion. this transition places the track-and-hold into hold mode and samples the analog input at this point. if the user does not want the AD7091 to enter power-down mode, convst should be taken high before the end of the conversion. a conversion requires 650 ns to complete. when the conversion process is finished, the track-and-hold returns to track mode. before the end of a conversion, pull cs low to enable the busy indicator (see figure 26). the conversion result is shifted out of the device as a 12-bit word under the control of sclk and the logic level of cs at the end of a conversion. at the end of a conversion, sdo is driven low. sdo remains low until the msb (db11) of the conversion result is clocked out on the first falling edge of sclk. db10 to db0 are shifted out on the subsequent falling edges of sclk. the 13 th sclk falling edge returns sdo to a high impedance state. data is propagated on sclk falling edges and is valid on both the rising and falling edges of the next sclk. the timing diagram for this operation is shown in figure 26. if another conversion is required, pull convst low again and repeat the cycle. three-state three-state cs sclk 1 5 12 2 34 db11 db10 db9 db2 db1 db0 t 2 t 4 t 3 t 5 t 6 db8 db7 sdo convst eoc notes 1. eoc is the end of a conversion. t 1 10 11 t 9 t quiet t 7 t 8 13 10494-024 figure 26. serial port ti ming with busy indicator
AD7091 data sheet rev. a | page 16 of 20 busy indicator disabled to operate the AD7091 without the busy indicat or , a conversion must first be started. a high - to - low transition on convst initi - ates a conversion. this transition p lace s the track - and - hold into hold mode and samples the analog input at this point. if the user does not want the AD7091 to enter power - down mode , convst should be taken high before the end of the conversion. a conversion requires 6 5 0 ns to complete. when the conversion process is finished, the track - and - hold returns to track mode . to prevent the busy indicator from becoming enabl ed, ensure that cs is pulled high before the end of the conversion (see figure 27 ) . the conversion result is shifted out of the device as a 12 - bit word under the control of sclk and cs . the ms b (bit db11) is clocked out on the falling edge of cs . db10 to db0 are shifted out on the subsequent falling edges of sclk. the 12 th sclk falling edge returns sdo to a high impedance state. after all the data is clocked out, pull cs high again. data is propagated on sclk falling edges and is valid on both the rising and falling edges of the next sclk. the timing diagram for this operation is shown in figure 27 . if another conversion is required , pull convst low again and repeat the cycle. t h r e e - s t a t e t h r e e - s t a t e c s s c l k 1 5 1 2 2 3 4 db11 d b 10 d b 9 d b 2 d b 1 t 2 t 3 t 5 t 6 d b 8 d b 7 s do convst eoc 1 0 1 1 t 10 t quiet t 7 t 8 t 4 t 11 d b 0 t 12 notes 1. eoc is the end of a conversion. 10494-025 figure 27 . serial port timing w ithout busy indicator
data sheet AD7091 rev. a | page 17 of 20 software reset the AD7091 re quires the user to initiate a software reset upon power - up. n ote that failure to apply the correct software reset command may result in a device malfunction. the timing diagram for the software reset operation is shown in figure 28. to issue a software reset, 1. start a conversion by pulling convst low. 2. read back the conversion result by pulling cs low after the conversion is complete. 3. between the second and eighth sclk cycles, pull c s high to short cycle the read operation. 4. at the end of the next conversion, the software reset is executed. as soon as a software reset is issued, the user can start another conversion by pulling convst low. interfacing w ith an 8 - /16 - bit spi bus it is also possible to interface the AD7091 with a conventional 8 - / 16- bit spi bus. performing conversions and reading results can be achieved by configuring the host spi interface for 16 bits, whic h results in providing an additional four sclk cycles to complete a conver - sion compared with the standard interface methods (see the b usy indicator enabled section and the busy indicator disabled secti on). after the 13 th sclk falling edge with the busy indicator enabled or after the 12 th sclk falling edge with the busy indicator disabled, sdo returns to a high impedance state. the additional four bits should be treated as dont care bits by the host. al l other timings are as shown in figure 26 and figure 27 , with t quiet starting after the 16 th sclk cycle. a software reset can be performed by configuring the spi bus for eight bits and performing the op eration described in the software reset section. t 8 convst t 7 short cycle read t 10 cs sdo eoc eoc/ software reset t 12 t 8 t 7 notes 1. eoc is the end of a co n version. sclk 1 2 8 7 6 t 5 t 3 10494-028 figure 28 . software reset timing
AD7091 data sheet rev. a | page 18 of 20 outline dimensions 1.70 1.60 1.50 0.425 0.350 0.275 top view 8 1 5 4 0.30 0.25 0.20 bottom view pin 1 index area seating plane 0.60 0.55 0.50 1.10 1.00 0.90 0.20 ref 0.15 ref 0.05 max 0.02 nom 0.50 bsc exposed pad p i n 1 i n d i c a t o r ( r 0 . 1 5 ) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 01-14-2013-c 2.10 2.00 sq 1.90 figure 29. 8-lead lead frame chip scale package [lfcsp_ud] 2.00 mm 2.00 mm body, ultra thin, dual lead (cp-8-10) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding AD7091bcpz-rl ?40c to +125c 8-lead lead frame chip scale package [lfcsp_ud] cp-8-10 92 AD7091bcpz-rl7 ?40c to +125c 8-lead lead frame chip scale package [lfcsp_ud] cp-8-10 92 eval-AD7091sdz evaluation board eval-sdp-cb1z evaluation controller board 1 z = rohs compliant part.
data sheet AD7091 rev. a | page 19 of 20 not es
AD7091 data sheet rev. a | page 20 of 20 notes ? 2012 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10996 - 0- 6/13(a)

▲Up To Search▲

Price & Availability of AD7091

	To Download AD7091 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .